Memory Pooling

Memory in the AI Era, Part 5: Exploring CXL Workloads

We examine how CXL is used in real workloads through KV cache offload, memory pooling, and memory tiering.

Where CXL sits in the memory hierarchy — a memory pool next to the CPU and accelerator coherency

Memory in the AI Era, Part 4: Understanding CXL

Next to the GPU, HBM and HBF fill the gap — but there’s another empty seat next to the CPU. We look at CXL, the new interface that fills the awkward gap between PCIe and DDR: its basic structure, device types, and the CXL product blueprints the big three memory vendors are drawing.