HyperAccel Tech Blog

CES 2026 Key Highlights from a 2025 Participant (feat. SAMSUNG, SK, LG) Hello! I’m Hyunjun Park from the HyperAccel ML Team. CES, which started in Las Vegas on January 6th, successfully concluded on January 9th. I participated in last year’s (2025) CES and operated the HyperAccel booth, and based on that experience, I’d like to review this year’s (2026) CES. Some might wonder why I’m posting this now instead of last year. ...

We explore the background of TPU’s emergence and analyze Google’s AI semiconductor strategy by examining its hardware and software architecture.

An overview of how NVIDIA GPUs evolved and how the Hopper architecture hides memory latency with massive parallelism.

The Motivation Behind Starting Our Tech Blog In our company’s SW group, we have a developer named Jaewoo Kim (Author, LinkedIn). Jaewoo is developing legato, a language for our HW kernel development. For several months, Jaewoo has been consistently requesting something from us. Shouldn’t we have a company tech blog? (from Jaewoo) Jaewoo mentioned that he had experience posting projects from his previous company on a tech blog, and thanks to those posts, many talented developers became interested in the company and even joined. ...

Building a Programming Language Before building a compiler, we need to define the language it will compile. A programming language isn’t just syntax and semantics—it’s the user interface between humans and computers. What Is a Programming Language? Abstraction is one of the core ideas in computer science. Without abstraction, interacting with computers would require understanding electrical signals, memory layout, registers, and countless hardware details. A programming language simplifies this complexity. It provides a human-friendly way to express ideas while hiding the low-level mechanisms that make them work. In this sense, a programming language functions as a UI for computing—a layer that lets us focus on building logic, applications, and systems, rather than manually manipulating hardware. ...

NAVER DAN 2025 Report Introduction Hello! I’m Sinhyun Park from the HyperAccel ML team. I’d like to share my thoughts after attending NAVER DAN 2025, held at COEX on November 6-7, 2025. Motivation for Attending The main objectives for attending this conference were: Gaining insights on scalable storage infrastructure: Beyond sharing data between nodes within a computing cluster, I wanted to acquire technical insights for building storage infrastructure that enables data exchange across different clusters. ...

Philosophy of SGLang Since the introduction of LLMs, they have been used to solve complex tasks in various fields—including problem-solving, code writing, and answering questions. Today, they are expanding their ability to be agentic, completing tasks users request without human interference. This requires a wide range of prompting techniques, such as skeleton of thought or tree of thought. In other words, we structure LLMs to follow certain patterns to fit our needs, and we require programmability to control and guide them to meet our requirements. ...

Crafting Compilers Compilers This will be a series of posts describing what compilers are, how they are crafted, and how to build your own compiler. Compilers are complicated (sort of) programs that translate high-level programs (written in English mostly) into binary formats that computers can understand. Engineering compilers means designing the way that programs are translated. Let’s first think about what “programs” are, and how they look. I would define a program as a sequence of instructions for hardware to execute. So at the base level, programs are just sets of instructions composed of “1"s and “0"s. One of the original forms of programs was the assembly language used for computers such as the IBM 360. Programmers in the old days wrote hardware instructions directly to make computers run mission-critical programs such as calculating the trajectory of space rockets or managing bank accounts. These directly expressed what the computer should do at each step, and programmers had to be aware of all the hardware details the computer had. They had to manually calculate register usage, memory state, and every hardware detail, or their program would malfunction and blow up their spaceships. ...

PyTorch Conference 2025 Report Introduction Hello, I’m Minho Park, Lead of the ML Team at HyperAccel. I attended the PyTorch Conference 2025 held in San Francisco on October 22-23, and I’d like to share my observations and insights. About HyperAccel HyperAccel is a company that designs AI chips for efficient inference of Large Language Models (LLMs). We have completed IP verification with FPGA, and our ASIC chip and server are scheduled for release next year. For ASIC, we plan to provide an SDK that supports PyTorch for inference, along with vLLM and Kubernetes support. ...